1. Field of the Invention
The present invention relates to a design technique for a semiconductor integrated circuit. More particularly, the present invention relates to a design technique for a semiconductor integrated circuit provided with a dummy pattern.
2. Description of Related Art
In a semiconductor integrated circuit, there may be dense and sparse wiring pattern regions in terms of design. That is, the regions where a density of a wiring pattern (hereinafter referred to as a “pattern density”) is high and low may exist. Such nonuniformity in the pattern density may cause various problems in a manufacturing process of a design circuit.
For example, in a CMP (Chemical Mechanical Polishing) process, there occurs a difference in polishing characteristics between the high and low pattern density regions. As a result, there occurs a phenomenon called “dishing” in which a surface of a wiring (e.g., Cu wiring) dishes. The dishing means reductions in flatness of the wiring and a film thickness, which causes variation and increase in a wiring resistance.
To suppress such a defect occurring during the manufacturing process, it is important to, in a circuit design phase, equalize the pattern density as much as possible. For this purpose, in addition to a circuit wiring pattern (signal wirings, power supply lines, ground lines and the like), a “dummy pattern” is generally added to a design layout (refer to Japanese Patent Publication JP-2004-39951A and Japanese Patent Publication JP-2006-60051A). The dummy pattern is a wiring pattern unnecessary for any function of the design circuit, and also referred to as a dummy wiring or dummy metal. By adding the dummy pattern, the pattern density can be more equalized to thereby suppress the dishing or the like from occurring.
Japanese Patent Publication JP-2004-39951A describes a technique for improving local uniformity of a wiring pattern. For this purpose, a layout region is divided into a plurality of division regions, and a dummy pattern is inserted between design patterns of the division regions.
Japanese Patent Publication JP-2006-60051A describes a method of forming a dummy pattern having a highly uniform coverage. According to the method, a dummy pattern formation region is divided into a plurality of dummy pattern formation unit regions. Then, a plurality of inspection regions each having an area larger than the dummy pattern formation region are set. The plurality of inspection regions partially overlap with each other. Subsequently, a tentative coverage of a dummy pattern formed in the dummy pattern formation unit region in the inspection region is calculated. The calculated tentative pattern coverages are averaged to determine a final pattern coverage. A dummy pattern having an area corresponding to the final pattern coverage is formed in the dummy pattern formation unit region.
As described above, to improve a yield of a semiconductor integrated circuit, it is important to preliminarily place the dummy pattern in the design phase. However, a time required for the dummy pattern placement processing increases as the design circuit is increased in size, which causes an increase in design TAT (Turn Around Time). For this reason, it is considered that the layout region is divided into a plurality of division regions. By executing the dummy pattern placement processing in parallel with respect to the plurality of division regions, the design TAT is supposed to be reduced.
Here, the inventor of the present application has recognized the following points. That is, if the layout region is divided without discretion and the dummy pattern placement processing is performed with respect to the plurality of division regions independently of each other, the following problem may be caused.
For example, a dummy pattern placed in a division region may be too close to a wiring pattern in the adjacent division region. That is, a design rule error (spacing error) may occur between patterns in division regions adjacent to each other. This is because the dummy pattern placement processing is performed for the respective division regions independently of each other.
Moreover, in order to stabilize an electrical characteristic of a dummy pattern to reduce noise, it is desirable that the dummy pattern placed is connected to a power supply line or ground line. Here, let us consider a case where a first dummy pattern is placed in a division region; a second dummy pattern is placed in the adjacent division region; and the first dummy pattern and the second dummy pattern are respectively connected to a power supply line and a ground line. However, at a boundary between the division regions, the first dummy pattern and the second dummy pattern may come into contact with or overlap with each other. In such a case, a short circuit occurs between the first dummy pattern and the second dummy pattern.
For such a problem, the inventor of the present application has proposed a method of designing a semiconductor integrated circuit which is disclosed in Japanese Patent Publication JP-2009-49341A. The design method includes: (a) dividing a layout region in which a wiring pattern is placed into a plurality of division regions; (b) determining, with respect to each of the plurality of division regions, a dummy pattern placement region included in the each division region; (c) adding a dummy pattern in the dummy pattern placement region of the each division region; and (d) coupling the plurality of division regions to which dummy patterns are added with each other. Here, the dummy pattern placement region is apart from at least one of boundaries between the each division region and adjacent division regions.
According to an embodiment described in Japanese Patent Publication JP-2009-49341A, when the dummy pattern placement region is determined, “division boundary shift processing” and “setback processing” are performed. First, it is checked whether or not a division boundary parallel to wiring tracks overlaps with some wiring track. If some division boundary overlaps with (correspond to) any of the wiring tracks, the division boundary is parallel translated to a location where the division boundary does not overlap with the wiring track. This is the “division boundary shift processing”. On the other hand, in the setback processing, with respect to each division region, a region having a size corresponding to the division region is reduced by a predetermined distance from a division boundary intersecting with a wiring track towards inside. The resultant region is set as the dummy pattern placement region. That is, the dummy pattern placement region is apart from the division boundary intersecting with the wiring track by the predetermined distance. The predetermined distance is, for example, a minimum wiring pitch (hereinafter referred to as a “first wiring pitch”) specified by a design rule.
As described above, according to Japanese Patent Publication JP-2009-49341A, the layout region is divided into the plurality of division regions. Accordingly, the dummy pattern placement processing can be performed “in parallel”. Moreover, the dummy pattern placement region in which the dummy pattern is placed is determined through the above-described “division boundary shift processing” and “setback processing”. As a result, after the division regions are coupled with each other, a design rule error or short circuit around the division boundary is prevented from occurring. That is, the design TAT can be reduced with suppressing the occurrence of the design rule error or short circuit.
The inventor of the present application has recognized the following points. According to Japanese Patent Publication JP-2009-49341A, the dummy pattern placement processing can be performed with respect to a plurality of division regions in a parallel distributed manner, and thereby a time required for the dummy pattern placing can be considerably shortened. That is, the design TAT is considerably reduced.
However, only in some special situations, a design rule error around a division boundary may occur. That is a case where a macro cell pattern or a thick wiring pattern is placed near an outside of a division boundary of some division region. A wiring pitch specified by the design rule for the macro cell pattern or the thick wiring pattern is hereinafter referred to as a “second wiring pitch”. In general, regarding the macro cell or the thick wiring, the second wiring pitch is set larger than the above-described first wiring pitch for a normal wiring pattern, in order to improve yield. In other words, it is necessary to ensure a larger wiring pitch than normal for the macro cell pattern or the thick wiring pattern. Therefore, even if a dummy pattern placement region is set back from a division boundary intersecting with a wiring track by the “first wiring pitch”, a design rule error may occur after the coupling of the division regions in the case where a macro cell pattern or a thick wiring pattern is placed near an outside of the division boundary.